ao68000 - Wishbone 68000 core

PRIOLITY LOW

I tested ao68000 by different simulator.

Veritak http://www.sugawara-systems.com/

OK.

Modelsim-Altera starter edition htp://www.altera.com/

There are some problems. A position defining a signal is bad. CODE use it before define. When I changed the place, simulation was possible.

I want you to revise it if there is the time that is enough for you.

---- modelsim message ----

Error: ao68000.v(1416): Undefined variable: pc_valid. Error: ao68000.v(1498): 'pc_valid' already declared in this scope (registers). Error: ao68000.v(1703): 'dn_byteena' already declared in this scope (memory_registers). Error: ao68000.v(2911): Undefined variable: micro_pc_0. Error: ao68000.v(2926): Undefined variable: micro_pc_1. Error: ao68000.v(2936): 'micro_pc_0' already declared in this scope (microcode_branch). ** Error: ao68000.v(2937): 'micro_pc_1' already declared in this scope (microcode_branch).

---- modelsim message ----

Thank you.

I commited a few fixes:

• the SEL_O signal is set to the required value when reading,
• I rearrange the code to fix the ModelSim errors,
• the Wishbone reset signal RST_I was changed to an asynchronous one: reset_n.

The commit was quite extensive, I hope I didn't introduce any new errors. I tested the design briefly.

Thank you for your ongoing tests.

Thank you for update. I try to it.

I am closing this request. The design simulates with quite a few warnings, but no errors.

Thank you for your tests.