Overview :: News :: Downloads :: Tracker :: Discussions (cores)

Wishbone FLASH Interface for Parallel FLASH: Overview Details Name: wb_flash Created: 03-Jun-2008 08:11:14 Updated: 20-Jul-2008 02:47:40 CVS: browse Other project properties Category :: Memory core Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Howard M. Harte Statistics view Description Wishbone to Parallel FLASH interface with integral wait-state generator. This design has been used with the Intel StrataFlash Xilinx Spartan 3E Starter Kit. Provides an 8-bit data interface to the FLASH, and a 32-bit Wishbone Slave Interface with byte enables. The StrataFlash on the S3E Starter Kit can be programmed using the PicoBlaze RS-232 StrataFlash™ Programmer downloadable from the following site: http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm Features Compatible with Intel StrataFlash J3 on Xilinx Spartan 3E Starter Kit Supports byte-mode operation. 32-bit Wishbone Slave Interface Status Tested on Xilinx Spartan 3E Starter Kit