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WISHBONE DMA/Bridge IP Core: Overview Details Name: wb_dma Created: 25-Sep-2001 10:15:03 Updated: 22-May-2007 11:50:52 CVS: browse Other project properties Category :: SoC Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Rudolf Usselmann Statistics view Opened bugs project has opened bugs Description This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces. Some of the main features are: Up to 31 DMA Channels 2, 4 or 8 priority levels Linked List Descriptors support Circular Buffer support FIFO buffer support Software & Hardware handshake support Automatic Channel Registers Reload support Fully configurable Please see the spec for more details ! Status 8/2/2001 Added another feature: Now you can backoff to the beginning of the current transfers (this is useful for things like Etherenet, where you might have to restart in case of collisions or errors). New Directory Structure ! We have agreed on a common directory structure at OpenCores. I will post a message to cores@o... each time I have an update Change log 8/2/2001 Added another feature, Directory Structure has changed 6/6/2001 RU Second Release 19/3/2001 RU Released Code 16/3/2001 RU Initial web page This IP Core is provided by: www.ASICS.ws - Solutions for your ASIC/FPGA needs -