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wb_ddr: Asynchronous DDR SDRAM controller: Overview Details Name: wb_ddr Created: 09-Feb-2007 20:03:06 Updated: 07-Jan-2008 13:19:31 CVS: no files in cvs Other project properties Category :: Memory core Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Joerg Bornschein Statistics view Overview wb_ddr is a DDR SDRAM controller with a Wishbone bus interface written in Verilog. It was originally build to support the Xilinx Spartan3E Starter kit which includes a Spartan3E-500 FPGA and 64MB DDR266 RAM, but is known to support other FPGAs from Xilinx. It should be easy to port to other vendors FPGAs - it currently uses two Xilix specific components: a DCM for frequency synthesis and ODDR2 output buffers. This is a asynchronous controller: The Wishbone interface and the DDR interface run at different clock rates. This allows great flexibility when designing systems and optimizes latency and bandwidth. This controller uses some RAM resources to implement a 2-way associative buffer cache to speed up DDR access. Getting it The most current version is managed in a Bazaar repository at https://roulette.das-labor.org/bzrtrac/wiki/wb_ddr/. You can download zip from OpenCores.org.