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WISHBONE Conmax IP Core: Overview Details Name: wb_conmax Created: 23-Oct-2001 04:55:03 Updated: 10-Feb-2004 03:58:32 CVS: browse Other project properties Category :: SoC Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Rudolf Usselmann Statistics view Description This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves Some of the main features are: Up to 8 Masters Up to 16 Slaves 1, 2 or 4 priority levels Fully configurable Example SoC with the CONMAX IP Core Status October 2002, Maintenance update: Fixed a typo in parameter passing and in the specification May 2002. Several users of the core have reported that the core performs as specified. Project is now considered completed. 10/19/2001 Initial Release. I will post a message to cores@o... each time I have an update Change log 10/19/2001 Initial Reslease This IP Core is provided by: www.ASICS.ws - Solutions for your ASIC/FPGA needs -