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USB 1.1 Host and Function IP core: Overview Details Name: usbhostslave Created: 30-Sep-2004 11:05:03 Updated: 22-Mar-2008 13:51:55 CVS: browse, lint reports Other project properties Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Steve Fielding Statistics view News Revision 1.3 is now available. This release is a bug fix. Fixes metastability and delay hazard issue in the front end module 'readUSBWireData'. This typically was causing occasional receive packets to be lost especially longer data packets. Many thanks to Mario Becroft for discovering this bug. Development Kit A complete usbhostslave Development Kit is now available; http://www.base2designs.com/DUSB-PHY.htm This consists of a Santa Cruz format daughter card that supports many development kits from Altera and Microtronix, along with pre-built hardware reference designs and full uCLinux support. Description USBHostSlave is a USB 1.1 Host and Function IP core. It supports full speed (12Mbps) and low speed (1.5Mbps) operation, and supports the four types of USB data transfer; control, bulk, interrupt, and isochronous transfers. USB Function has four endpoints, each with their own independent FIFO. All FIFO depths configurable via parameters. It has a 8-bit Wishbone slave bus interface. All the state machines have been designed using ActiveHDL FSM2HDL, so they are easily readable and understandable, but it is still possible to edit the Verilog RTL if so desired. Graphical state diagrams are used because they are much easier to understand than just RTL source code. Graphical state diagrams ease creation, maintenance, documentation, and re-use, of FSMs. Aldec ActiveHDL is an excellent tool for creating graphical state diagrams, only requiring a single .asf file per state machine module. This makes it easy to maintain the FSMs and incorporate them into your existing text based module hierarchy. For those who are targeting Altera FPGAS, and prefer to start from a pre built component, there is a Quartus SOPC Builder component available for download, along with a HOW-TO doc that explains how to integrate the component into a Quartus project. The SOPC component has been tested on the Altera NIOS development board, Cyclone edition, and requires a custom Santa Cruz daughter card. See downloads section for full schamatics and bill of materials. http://www.opencores.org/pdownloads.cgi/list/usbhostslave Features USB 1.1 Host and Function Full and low speed. Control, bulk, interrupt, and isochronous transfers FIFO interface FIFO depth configurable. Automatic SOF generation 8-bit Wishbone interface Status Version 1.2 is now available. This release is mainly a clean up, and also sees the release of a full SystemC test bench. Design has been tested via simulation with SystemC test bench. The SystemC test bench is available as part of a complete Aldec Active-HDL project. Since the majority of the SystemC test bench is generic C++, the same test bench can also be used for hardware testing by simply replacing the SystemC port instances with regular C++ class methods. See http://www.opencores.org/projects.cgi/web/usbhostslave/NIOSsoftware.zip Initial hardware testing completed using an Altera NIOS2 development kit Cyclone edition, and a Santa Cruz USB transceiver daughter card. Completed loop back tests between two instantiations of the core, one configured as a host and the other as a function. Also performed limited host mode testing with a full speed USB flash drive, and low speed USB keyboard. Tested uClinux driver, with flash drive, and 80GB hard drive. To do. Still need to test isochronous mode, pre-amble mode, and all host mode features related to accessing a low speed device via a hub. Synthesizable under Quartus 6.0 SP1. Uses approximately 2700 logic cells in an Altera Cyclone EP1C20. If you only require host, or function support, then removal of the unwanted logic should reduce the core to around 1600 logic cells. Acknowledgements Many thanks to Aldec http://www.aldec.com for support with Active-HDL, and T3 Technical Sales, and Arrow Electronics for support with Altera FPGAs, and Microtronix for Linux support. Known Issues Bus-turn-around time is compliant with low speed, but not full speed USB 1.1 specification. The USB 1.1 spec requires host or device to provide a response within 6.5 bit times in both full and low speed modes. Operating with a system clock of 48Mhz, usbhostslave currently provides a response within 1uS (12 full speed bit periods, 1.5 low speed bit times). The USB 1.1 specification takes into account the worst case system configuration of 5 cascaded hubs, and 6 maximum length cables (see figure 7-31 in USB 1.1 spec), resulting in a worst case system bus-turn-around time of 16 full speed bits. So, operating with a system clock of 48MHz, usbhostslave will be within full speed system spec for 2 cascaded hubs, and 3 maximum length cables. Increasing clock speed to 96MHz would make the core USB 1.1 compliant. Help Wanted I need help creating an open source usb driver that could be used with systems that have either a simple OS or no OS. Initially it would only need to support USB flash drives, and could be derived from the USB drivers that come with U-boot. If you would like to volunteer, let me know, and I can give you more details.