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Ultimate CRC: Synthesis FPGA synthesis results The table below shows synthesis results for different data widths for two targets. Notice that exact numbers depends on tool used, tool settings and target. Generics used are: POLYNOMIAL = "00000100110000010001110110110111" (CRC-32: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1) INIT_VALUE = "11111111111111111111111111111111" DATA_WIDTH - according to table SYNC_RESET = 0 Target: Xilinx Virtex4 FX Target: Altera StratixII Data Width Slices Max freq. (MHz) Throughput (Gbps) ALUT's Max freq. (MHz) Throughput (Gbps) 1 22 349 0.349 33 399 0.399 2 26 349 0.698 38 327 0.654 4 26 325 1.300 40 269 1.076 8 38 309 2.472 53 272 2.176 16 64 246 3.936 72 231 3.696 32 130 162 5.184 165 169 5.408 64 319 93 5.952 357 91 5.824 128 842 55 7.04 761 43 5.504 256 2209 28 7.168 1544 23 5.888