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Turbo Decoder: Overview Details Name: turbocodes Created: 16-Feb-2005 11:40:12 Updated: 14-Jun-2005 16:54:05 CVS: no files in cvs Other project properties Category :: ECC core Language :: VHDL License :: LGPL Development status :: Beta Project maintainers David Brochart Statistics view Description This project features a double binary, DVB-RCS turbo decoder using the SOVA algorithm. Two models are included: a MyHDL model, along with a complete testbench, a synthesizable VHDL model. Features Double binary, DVB-RCS code Soft Output Viterbi Algorithm MyHDL cycle/bit accurate model and testbench Synthesizable VHDL model Status Release 0.3: Synthesizable VHDL model Fixed ponderation filtering Release 0.2: DVB-RCS interleaver DVB-RCS puncturing (decoder only) Controllable SNR for the noiser Release 0.1: MyHDL model posted Simulation system consists of a random data pattern generator, turbo coder, transmission channel (gaussian noiser with controlable standard deviation), turbo decoder and Bit Error Rate monitors Turbo decoder generic parameters are: number of iterations, number of bits for the coding of the systematic and redundant data in the decoder, number of bits for the coding of the extrinsic information, first and second trellis' length, number of bits for the coding of the accumulated distances, length of the interleaver matrix side No puncturing No coder/decoder synchronization No wishbone I/F No in-operation BER monitoring Simple line-write/column-read interleaver Basic documentation (block diagrams) Results Decoder input signal width: 4 bits Extrinsic information signal width: 5 bits First trellis' length: 24 Second trellis' length: 12 Accumulated distances signal width: 9 bits Interleaver frame size: 64 bit couples Signal-to-noise ratio: 5.1 dB Code rate: 1 / 2 Bit Error Rate: 0.0368951613 @ iteration 0 (no decoding) 0.0027355688 @ iteration 1 0.0001380629 @ iteration 2 0.0000722789 @ iteration 3 0.0000255319 @ iteration 4 0.0000212947 @ iteration 5