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TDM controller: Overview
Features
- 8 bit parallel backend interface
- Needs external Framer
- Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit rate 2.048Mbps)
- Supports ST-Bus (Serial Telecom bus) interface.
- Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory.
- Supports read for all or partial TDM slots from the ST-bus.
- Supports write for all or partial TDM slots to ST-bus.
- Supports two serial lines one input and one output.Mli>9. It supports N×64 mode (i.e. it supports sampling (or writing) to N consecutive time slots)
- Supports two serial lines one input and one output.
- Can be connected to other ST-Bus compatible devices via serial or star configurations.
- If no data is available for transmission it sends all ones.
- Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.
- Optional External FIFO buffer, configuration and status registers.
- The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel.
- ISDN (2BD) support can be supported by adding three parallel HDLC controllers on the first three time slots.
- For complete specifications refer to spec document
Core top block diagram
Status
- Code is ready for both TDM and ISDN controllers in the OpenCores CVS (see Download section).
- Need help in verfying the design.
Resource usage
TDM core: which includes ST-Bus interface that inserts/samples 32 channels and does the conversion between serial and parallel representation.
| Vendor |
Device |
Size |
Frequency |
Board Tested |
Functional Test |
Notes |
| Altera |
EP20K100EBC356-3 |
130LCs |
CLK_I(backend)=139.06MHz |
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- |
No optimization was peroformed, using Quartus II |
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