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T51 mcu: Overview Details Name: t51 Created: 25-Apr-2002 19:15:55 Updated: 10-Apr-2007 23:08:16 CVS: browse Other project properties Category :: Microprocessor Language :: VHDL Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Andreas Voggeneder Daniel Wallner Statistics view Description 8052 compatible microcontroller core. Two different top levels: T8052: Single cycle synchronous RAM/ROM Wishbone bus interface for memory mapped peripherals T8032: Wishbone bus interface A utility to create VHDL ROMs is also included. To create a ROM compatible with the 8052 core type: hex2rom [-b] inputfile.hex ROM52 13b8s > ROM52.vhd Leonardo Spectrum can infer the ROMs created with hex2rom to Xilinx block RAM. I have also modified the baud rate recognition of the BASIC-52 ROM to support the faster instruction timing. The modified BASIC-52 might also work with other high speed 8032 compatible cores such as the 80c320. Browse source code here. Download latest tarball here. Features All peripherals/interrupts implemented Single cycle per byte fetch Supports synchronous RAM/ROM Single cycle MOVX (8052) Optional second DPTR Technology independent Three stage pipeline Status Completed and verified on xilinx and altera fpga