Overview :: News :: Downloads :: Tracker :: Discussions (cores)

SystemC/Verilog DES: Overview Details Name: systemcdes Created: 02-Jul-2004 23:36:37 Updated: 19-Sep-2005 11:15:43 CVS: browse Other project properties Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Javier Castillo Villar Statistics view Description SystemC DES is a implementation of the DES algorithm in SystemC focusing on low area applications. Implements the encoder and decoder in the same block. It was fully verified using TLM (Transaction Level Modelling Style) defined in the SystemC Verification Library. Verilog translation for synthesis is also provided. The core was tested on a Virtex2 FPGA succesfully. This work is given by Universidad Rey Juan Carlos (Spain) www.escet.urjc.es/~jmartine Features SystemC and Verilog code are provided Verified using TLM(Transaction Level Modelling Style) Encoder and decoder in the same block Synthesis Results: Comparation between SystemC DES project and DES IP project Synthesis results for a Xilinx XC2V1000FG456-4 DES IP Area: 11% Freq.: 167 Mhz Cycles per block: 16 SystemC DES Area: 4% Freq.: 90 Mhz Cycles per block: 16 If you need a more troughput choose DES IP core. If you need less throughput but want half area choose SystemC DES Status Writing documentation