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128/192 AES: Overview Details Name: systemcaes Created: 02-Jul-2004 23:36:46 Updated: 19-Sep-2005 11:16:06 CVS: browse Other project properties Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Javier Castillo Villar Statistics view Description Here you can find two different implementations of AES encryption algorithm: A 128 bits AES algorithm focusing on very low area applications. A 192 bits AES algorithm focusing on very low area applications. The 128 bits low area implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bits low area implementation takes about 280 cycles to encrypt/decrypt a block. They don't use memories to store the S-box and have many other architectural improvements to reduce the area comsumption. Implements the encoder and decoder in the same block. The cores were written in SystemC RTL, and verified using TLM(Transaction Level Modelling Style). Verilog synthesizable code is also provided All implementations have been tested on a Xilinx Virtex2 FPGA succesfully. Features SystemC and Verilog code is provided Verified using TLM(Transaction Level Modelling Style) Encoder and decoder in the same block This work is given by Universidad Rey Juan Carlos (Spain) www.escet.urjc.es/~jmartine Status 128 bits low area implementation uploaded 192 bits low area implementation uploaded