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SystemC/Verilog Random Number Generator: Overview Details Name: systemc_rng Created: 19-Aug-2004 13:27:50 Updated: 20-Mar-2008 13:33:43 CVS: browse Other project properties Category :: Other Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Javier Castillo Villar Statistics view Opened bugs project has opened bugs Description A SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statisticall properties. Based on the Thomas E. Tkacik work available at: http://ece.gmu.edu/crypto/ches02/talks_files/Tkacik.pdf This work is given by Universidad Rey Juan Carlos (Spain) www.escet.urjc.es/~jmartine Features Very good statisticall properties Synthesizable Status Done