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Single Slot PCM Interface: Overview Details Name: ss_pcm Created: 17-Sep-2002 15:50:22 Updated: 10-Feb-2004 03:56:08 CVS: browse Other project properties Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Rudolf Usselmann Statistics view Description Simple PCM Interface. Allows to interface to such popular devices like TI DSPs (via McBSP bus) in PCM mode. Of course many more applications. Very small and simple core. Features Implemented in Verilog Frame Start position adjustable full 16 bit frames 1 Receive holding register 1 Transmit holding Register Fully Synthesisable Can handle PCM streams at any rate, 128KHz to 100MHz. 38 LUTs in a Spartan II Status This core is fully functional and completed. It was tested on a XESS XCV800 board interfacing to a proprietary device with a TI DSP, exchanging PCM streams in both directions. This IP Core is provided by: www.ASICS.ws - Solutions for your ASIC/FPGA needs -