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srl_fifo: Overview Details Name: srl_fifo Created: 02-Jan-2008 19:35:41 Updated: 28-Mar-2008 21:43:33 CVS: browse Other project properties Category :: Memory core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable Project maintainers Andrew Mulcock Statistics view Description Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's. Built to be small. In a Spartan 3, the 8 bit wide , 16 bit deep FIFO utilises 19 Luts of which 8 are used as SRL, 11 as Logic. Features Pure VHDL, no instantiated components, all inferred small size Status Simulated and ( 16 and 32 ) programmed into a Spartan 3 FPGA Synthesised with ISE 10.1 looking at a generic srl fifo now ise can handle such