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SD/MMC Controller: Overview Details Name: spimaster Created: 11-Apr-2008 07:49:43 Updated: 05-Nov-2008 17:30:11 CVS: browse Other project properties Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Steve Fielding Statistics view Opened bugs project has opened bugs News Release 1.2 now available. New version modifies read timing which was marginal for some SD cards. Description SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple Fifo interface. Provides transfer speeds up to 24Mbps. If combined with the fpgaConfig project: http://www.opencores.org/projects.cgi/web/fpgaconfig/overview then it is possible to configure an FPGA from SD memory. If the FPGA configuration includes this core (spiMaster) and a softcore processor, then the processor can copy a software image from SD memory into RAM, and then execute from RAM. Thus a complete FPGA softcore processor can be implemented with just an FPGA, DRAM, and SD card. See fpgaConfig used in a complete project at: http://www.opencores.org/projects.cgi/web/openriscdevboard Features Simple interface to SD cards up to 2GB SD Initialization SD 512 byte block write SD 512 byte block read Data access up to 24Mbps 8-bit Wishbone slave interface Separate Wishbone and core logic clocks Simulation files 900 logic cells in Altera Cyclone2 Status Tested in FPGA. The following mods and additions could be useful: Interrupt line. Card detect. Master wishbone interface would be nice, so that DMA transfers to memory could be performed. SD/MMC memory card simulation model needs improvement. The model does not parse the commands from the core, and does not provide any storage. Multiple SPI chip select support. Larger Fifos to allow simultaneous processor and core Fifo access.