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SPDIF Interface: Synthesis FPGA Synthesis results Resource utilization for a minimum version and an all-bells-n-whistles version of the SPDIF cores are shown below for two popular FPGA targets. Exact numbers will depend on tool used, tool settings and target architecture. Recevier SPDIF Receiver Altera Cyclone Xilinx Spartan 3 Minimum: DATA_WIDTH = 16 ADDR_WIDTH = 8 CH_ST_CAPTURE = 0 WISHBONE_FREQ = 33 203MHz 401 LE's 2,048kbit ram 110MHz 246 slices 18,432kbit ram All features: DATA_WIDTH = 32 ADDR_WIDTH = 13 CH_ST_CAPTURE = 8 WISHBONE_FREQ = 33   156MHz 2259 LE's 131,072kbit ram 67MHz 1376 slices 147,456kbit ram Transmitter SPDIF Transmitter Altera Cyclone Xilinx Spartan 3 Minimum: DATA_WIDTH = 16 ADDR_WIDTH = 8 USER_DATA_BUF = 0 CH_STAT_BUF = 0 196MHz 239 LE's 2,048kbit ram 82MHz 141 slices 18,432kbit ram All features: DATA_WIDTH = 32 ADDR_WIDTH = 13 USER_DATA_BUF = 1 CH_STAT_BUF = 1   85MHz 1477 LE's 98,304kbit ram 36MHz 1046 slices 110,592kbit ram