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Single Port ASRAM: Overview
| Details Name: single_port
Created: 07-Jan-2003 09:40:50
Updated: 17-Nov-2007 13:53:00
CVS: browse Other project properties Category :: Memory core
Development status :: Production/Stable
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Description
The main purpose of this project was two-fold. The first purpose was to implement a client-server test architecture based on Bergeron's work in VHDL. The main advantage to this verification method is greater stress-test ability and removes the need to create test script language to test the DUT.
The second purpose was to bench-mark the running speed of the ASRAM implemented as three different architectures.
1. Linked-list
2. Bit-vector
3. regular std_logic_vector implementation.
Features
- Demonstrates client-server testbench architecture in VHDL.
- bit-vector array memory core
- standard-logic array memory core
- dynamic linked-list memory core.
Status
Completed.
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