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Simple Programmable Interrupt Controller: Overview Details Name: simple_pic Created: 02-Dec-2002 13:30:27 Updated: 04-Mar-2008 19:27:25 CVS: browse Other project properties Category :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Richard Herveille Statistics view Description Simple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable per interrupt source. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances. Very simple, very small. Features Up to 8 interrupt sources Sensitivity (edge/level) programmable per interrupt source Polarity programmable per source Static synchronous design Fully synthesisable 48 LUTs in a Spartan-II, 83 LCELLs in an ACEX Status Design is finished and available in Verilog from OpenCores CVS.