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Simple General Purpose IO: Overview Details Name: simple_gpio Created: 02-Dec-2002 13:30:29 Updated: 14-Feb-2004 14:10:01 CVS: browse Other project properties Category :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Richard Herveille Statistics view Description Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface). Very simple, very small. Features Up to 8 GPIO pins per core Each GPIO pin individually programmable as either input or output Static synchronous design Fully synthesisable 11 LUTs in a Spartan-II, 43 LCELLs in an ACEX Status Design is finished and available in Verilog from OpenCores CVS.