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Simple-CPU SC91-A: Overview Details Name: simple-cpu Created: 06-Oct-2005 12:48:39 Updated: 07-Oct-2005 08:19:23 CVS: not found! Other project properties Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha Project maintainers Paul Pinault Statistics view Description Simple-CPU is a 32 bits RISC processor with linear memory access using load and store methods. It is based on as less as possible instructions with lots of parameters. This document will so describe natural cpu language with its encoding and then describe a user friendly assembly set of instructions that alias natural one. Simple-CPU has 32 double word registers (32b width) named R00 to R31. twenty nine of them are for general use. R00 is resserved for program counter, R01 for stack pointer and R02 is used for flags and specific status or conf bits. R00 and R02 can be used in all instruction like general ones. All instructions are 32 bits len even if they need less. All instructions need 1 cycle including instruction loading. There is no distinction between program space and data space into memory. Instructions allways start on a 4 modulus address but data access can be done by byte, word or double word. See http://www.simple-cpu.com for more information until open-core cvs will be commited with the first beta version. Features see http://www.simple-cpu.com Status Creating instruction set and documentation - Ending General architecture document - Running CPU core coding and tests - Running CPU interfaces and wishbone - To do Adding peripherical - To do Assembly compiler - Planed end of 2005 Java simulator - Planed first trimester 2006 Loader coding - To do GCC porting - Planed first trimester 2006