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SystemC to Verilog Synthesizable Subset Translator: Overview Details Name: sc2v Created: 08-Oct-2004 14:44:07 Updated: 19-Mar-2007 13:02:53 CVS: browse Other project properties Category :: Other Phaze :: Design done Development status :: Production/Stable Project maintainers Pablo Huerta Javier Castillo Villar Statistics view Description The sc2v translator is a software tool that translates a SystemC RT description into a Verilog equivalent one. The sc2v translator is based on lex and yacc tools. You need lex and yacc installed in order to compile sc2v. This work is given by Universidad Rey Juan Carlos (Spain) www.escet.urjc.es/~jmartine Features Full source code PDF documentation Written using lex and yacc tools Status Version 0.5 TODO: See README File LOOKING FOR CONTRIBUTORS