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Simple Asynchronous Serial Controller: Overview Details Name: sasc Created: 17-Sep-2002 15:50:02 Updated: 30-Mar-2006 04:47:07 CVS: browse Other project properties Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Rudolf Usselmann Statistics view Description Simple asynchronous serial controller (aka UART). Includes 4 byte receive and a 4 byte transmit FIFO (FIFO size can be easily adjusted). External baud rate generator (included). Very small. Features Implemented in Verilog Flow Control (CTS/RTS) 1 start bit, 1 stop bit, NO parity 4 byte receive FIFO 4 byte transmit FIFO Fully Synthesisable 102 LUTs in a Spartan II Status This core is fully functional and completed. It was verified in hardware in an XESS XVC800 FPGA prototype board with a Maxim RS232 line driver. This IP Core is provided by: www.ASICS.ws - Solutions for your ASIC/FPGA needs -