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PIF2WB: Overview Details Name: pif2wb Created: 04-Aug-2007 02:41:29 Updated: 07-Aug-2007 18:47:55 CVS: browse Other project properties Category :: SoC Language :: VHDL Phaze :: Design done Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Project maintainers Sergio Tota Statistics view Description This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration. Features PIF master support Wishbone slave support Burst transfers support VHDL RTL Fully synthesisable Status RTL: Complete Document: Complete