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OpenRisc Development Board: Overview Details Name: openriscdevboard Created: 11-Apr-2008 07:49:07 Updated: 03-May-2008 14:37:43 CVS: no files in cvs Other project properties Category :: Prototype board Development status :: Production/Stable Project maintainers Steve Fielding Statistics view Description Opensource OpenRisc Development Board. All CADsoft Eagle design files available to recreate the board using EagleLite, a freeware PCB design tool. Uses the largest Cyclone 2 device available in a QFP package, thus allowing larger RTL designs to be ported, and at the same time allowing easier PCB design and board assembly. Board design is double sided, and can be manufactured using low cost batch PCB services. A complete system consists of three separate boards; Main board that contains the FPGA, SDRAM, regulators, Santa Cruz expansion header, and config expansion header. Config board containing SD card slot, SPI flash, C8051, fpgaConfig header, JTAG header, and OpenRisc debug header. Santa Cruz daughter card containing RS-232 transceiver, and DB9 connector. It also has support for dual USB, and dual Ethernet, but these are untested. A complete FPGA project is available for the board set. This includes a minimal OR1K, SDRAM memory controller, UART peripheral, and SD memory interface. Simulation is possible using Icarus Verilog simulator, and the design can be compiled under Altera Quartus. Software is available to demonstrate copying a software image file from SD flash memory to SDRAM, and then executing the copied image. See fpgaConfig project for details of configuring FPGA from SD flash memory: http://www.opencores.org/projects.cgi/web/fpgaconfig/overview You can use this project as a basis for a compact OpenRisc implementation. A complete OpenRisc implementation requires just an FPGA, SDRAM, microSD card, and a tiny C8051. Features Eagle design files compatible with free Eagle Lite http://www.cadsoft.de/ Simple PCBs can be manufactured using batch PCB services. No BGA devices Large FPGA (20,000 logic cell Altera Cyclone 2) Single 16MByte x32 SDRAM Santa Cruz expansion header. Support for fpgaConfig http://www.opencores.org/projects.cgi/web/fpgaconfig Support for SD/MMC controller http://www.opencores.org/projects.cgi/web/spimaster Status OR1K running on board, and able to copy software image from SD flash TO SDRAM, and execute. Santa Cruz expansion board requires more testing. Documentation needed.