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Memory Controller IP Core: Overview Details Name: mem_ctrl Created: 25-Sep-2001 10:15:03 Updated: 22-May-2007 11:49:06 CVS: browse Other project properties Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Rudolf Usselmann Statistics view Description This is a advanced Memory Controller intended for embedded applications. Some of the features are: SDRAM, SSRAM, FLASH, ROM and many other devices supported 8 Chip selects, each uniquely programmable Flexible timing to accommodate a variety of memory devices Burst transfers and burst termination Performance optimization by leaving active rows open Default boot sequence support Dynamic bus sizing for reading from Async. Devices Byte parity Generation and Checking Multi Master memory bus support Industry standard WISHBONE SoC host interface Up to 8 * 128 Mbyte memory size Supports Power Down Mode Status May 2002, The core has been verified in hardware. This project is now completed. 8/2/2001 I have fixed various bugs and made many small changes and am still trying to improve and debug the memory controller further. New Directory Structure ! We have agreed on a common directory structure at OpenCores. I will post a message to cores@o... each time I have an update This IP Core is provided by: www.ASICS.ws - Solutions for your ASIC/FPGA needs -