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MCPU - A minimal CPU for a CPLD: Overview Details Name: mcpu Created: 31-Jul-2007 15:17:33 Updated: 21-Mar-2008 16:32:28 CVS: no files in cvs Other project properties Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable Project maintainers Tim Böscke Statistics view MCPU - Minimal CPU for a 32 Macrocell CPLD MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation. Please let me know if you find a good use for this CPU and put your project/publication/lecture notes on the web. I will try to maintain a list here. I know it already has found good use for many purposes. Features The CPU is accumulator based and supports a bare minimum of registers. The accumulator has a width of eight bits and is complemented by a carry flag. The program counter (PC) has a width of six bits which allows addressing of 64 eight bit words of memory. The memory is shared between program code and data. Status v1.06 - latest revision, updated email address. v1.06b - fixed title Documentation (pdf) Project archive (Zip)