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M1 Core: Overview Details Name: m1_core Created: 03-Jan-2007 15:56:16 Updated: 07-Nov-2008 14:40:09 CVS: browse Other project properties Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Beta Project maintainers Fabrizio Fazzino Statistics view M1 Core briefly... The M1 Core is a 32-bit RISC CPU compatible with a popular GCC target. It's been designed for simplicity and it's been used for some didactical activities at the University of catania. The CPU is written in Verilog and it's been tested on FPGA (Xilinx Spartan-3E Starter Kit). The CVS tree includes sources from other two OpenCores projects: wb_ddr developed by Joerg Bornschein ps2_interface developed by John Clayton