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Internal Logic State Analyzer: Overview Details Name: log_anal Created: 26-Nov-2002 15:27:25 Updated: 11-Dec-2002 18:58:25 CVS: browse Other project properties Category :: Prototype board Standard :: Wishbone compliant core Development status :: Beta Project maintainers Ernest Jamro Statistics view Description The internal Logic state Analyser (LA) is a simplified version of a standard logic state analyzer, however it is build-in the prototyped circuit and therefore allows for probing internal signals. The LA at first writes probed signals into its internal memory, and then allows for off-line transfer through WISHBONE bus to a PC where the probed data can be watched. As during design prototyping watched signals are very often changed, the LA is mainly intended for FPGAs and works similarly to Xilinx ChipScope. Features Internal memory for on-line data probing and off-line probed data transfer. Generic number of probed signals : 8, 16 or 32 bits. Generic depth of acquired data (internal memory size) (16 to 64k). Software programmable single trigger value (and don’t care). Software programmable trigger place. Separate trigger bus with generic width 1 to 32 bits. Acquired data and trigger clock enable. Generic single or double clock operation (separate or not clock for data acquisition and system interface). WISHBONE compatible. Status done but testing is still required