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Lightweight 8080 compatible core: Overview
| Details Name: light8080
Created: 25-Oct-2007 00:39:29
Updated: 19-Aug-2008 03:58:39
CVS: browse Other project properties Category :: Microprocessor
Language :: VHDL
License :: GPL
Phaze :: FPGA proven
Development status :: Alpha
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Description
This is a simple, small microprogrammed 8080 core. There are already at least two other 8080-compatible cores in Opencores, both of them well proven. This one is different because it emphasizes area instead of cycle-count compatibility or speed.
I have tried to minimize size and complexity as much as possible, to the expense of speed. At about the same size as a Picoblaze on a Spartan 3 (197 LUTs + 1 BRAM), this is perhaps amongst the smallest 8-bit CPU cores available. On the other hand, it is rather slow in clock frequency and particularly in cycles per instruction (up to 50% more clocks per instruction than the original, which is an awful lot! -- see the design notes). Besides, the 2 KBytes of dedicated fpga ram it does use may in some designs be more valuable than a large number of logic blocks. The source is quite simple: a single file with less than 1300 lines of straightforward, moderately commented VHDL code; plus a microcode source file from which the microcode table embedded into the vhdl was assembled. A description of the circuit and its microcode is included in the design notes and the respective source files. However, the simplicity may be deceptive; it can be argued that the complexity of the system has been moved from the RTL to the microcode...
This is just a fun project I created to learn vhdl; my design goal was to get the simplest possible 8080-compatible core, at the smallest possible size, at any reasonable speed. And above all, at a minimum cost in development time -- so I could get something worthy done in the very limited time available.
Though I think I accomplished my goal, the resulting core is probably of little practical use: it is certainly no match for a picoblaze in its application niche, and it is not small enough to compensate for its lack of features (the smallest Nios II is only 2 or 3 times larger). And there are better 8080 cores around, as I said.
But if for any reason you happen to need a small 8080 compatible core, this one is about as small as it gets.
I am in debt with Scott A. Moore for his cpu8080 core. Though I have not used his code in this project, I studied it and did use much of the research and test material that he made available at this site.
Features
- Microcoded design, very simple circuit.
- Microcode source and assembler included, though the vhdl microcode table can be edited directly.
- Slower than original in clocks per instructions (up to 50%, comparative table included in the design notes).
- 100% binary compatible to original 8080.
- Uses positive clock edges only.
- Signal interface very simplified. Not all original status info available (no M1, for instance).
- Synchronous memory and i/o interface, with NO WAIT STATE ability.
- INTA procedure similar to original 8080, can use any instruction as int vector.
- Unimplemented intructions are NOPs.
Performance: - Xilinx XST on Spartan 3:
- 197 LUTs plus 1 BRAM @ 80 MHz (optimized for area)
- 225 LUTs plus 1 BRAM @ 100 MHz (optimized for speed)
- 615 LUTs @ 53 MHz (optimized for area, no block ram)
- Altera Quartus on Cyclone 2:
- 369 LEs plus 4 M4Ks @ 67 MHz (balanced optimization)
Status
Update, 8-18-2008:
A microcode bug has been found in INR M that the test bench did not catch. I've just checked in a corrected version (Thanks to Tomasz Olszewski for the accurate bug report!).
See the bug report in the tracker for the details. The project needs a much stronger test bench before upgrading to beta status.
Summary (8-28-2008):
The core has executed a functional test and some original code in hardware. Exhaustive tests, execution of large original software and interrupt response demo in hardware still to be done.
The core has passed a functional test, the 'Kelly Smith test', both in simulation and in hardware. Though the Kelly test is by no means exhaustive, I am now pretty confident that the design is sound and no big errors are going to show up (I do expect to find microcode bugs yet). The Kelly Smith test is a 8080 CPU test created in 1980 which tests for most flags, modes and instructions (excludes i/o, interrupt response and does not test all postconditions of all instructions). Though it is not an exhaustive test, it is quite complete and has been an invaluable help in the development. I have used the Kelly test version found in Scott Moore's cpu8080 core site, slightly modified to fit my hardware set up. I have built a small simulation-only test bench (vhdl/test/light8080_tb0.vhdl) which includes the Kelly tests and can be used as a regression test of sorts. The core has executed the kelly tests test code on two hardware incarnations: a Spartan 3 and a Cyclone 2, both at 50MHz (sources similar to simulation test bench, not included). In both cases they worked at first trial without glitches or funny behaviours. Yet, there was at least one hidden bug which I only detected after running the scs-1 monitor (a microcode bug).
Besides, I have built a sketchy 'demo': a slightly modified SCS1 monitor running on a Cyclone 2 starter board using internal fpga ram only and a serial port (again, I took the idea from Scott Moore, which did a similar but more complex test on his core). This demo uncovered a bug which was not detected by the Kelly tests (INR CY flag), and otherwise was successful. The SCS1 monitor is another piece of original 8080 code I found at Mr. Moore's cpu8080 site. It is a monitor/assembler, very useful in this type of situation when you don't trust your hardware yet. I have included my modified sources, its original documentation and the files necessary to set up the demo; though it will take some work to adapt it to other development boards or hardware configurations. I have been tinkering with the core a bit and there seems to be nothing wrong going on with it. Therefore I think I can put the project in 'alpha' status.
NOTE:
Interrupt response has not yet been tested in hardware, and the core hasn't yet executed any large piece of original software or any exhaustive functional test. The core will remain in alpha status until I sort this out.
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