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JPEG Hardware Compressor: Overview Details Name: jpeg Created: 03-Jan-2005 07:18:52 Updated: 25-Feb-2008 15:28:11 CVS: browse Other project properties Category :: Video controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Victor Lopez Lorenzo Statistics view Description This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with CIF resolution: 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. Download the code and try it, it's easy. The source code is VHDL and it is LGPL, so it can be used in commercial applications as long as the terms of the license are respected. Anyone interested in the image standards used in this project, they can be downloaded from the following places: JPEG (ITU-T81 standard): http://www.w3.org/Graphics/JPEG/itu-t81.pdf JFIF (JPEG file headers): http://www.w3.org/Graphics/JPEG/jfif3.pdf BMP (bitmaps for the testbench): http://netghost.narod.ru/gff/vendspec/micbmp/bmp.txt Please note that there is another Tab in this web page named "Detailed Description" with further info on this core. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: galland at opencores.org Features JPEG (ISO standard compliant and ITU-T81 compliant) Baseline DCT Huffman Encoding JFIF Header Three quantization (compression) levels Hardware resources (included in source) Xilinx Coregen DCT core (2D Forward DCT) SP BlockRAM memories (11, not counting memory for final compressed image) Total LUTs: 3969 (38% of XC2V1000-4) Clock Freq: 41.2 MHz for XC2V1000-4 Status 14/Mar/2005 : New directory structure for source files. Updated source code thanks to Peter Eisemann to include fixes to allow correct simulation under ModelSim. (Functionality has not changed). 03/Jan/2005 : Project posted. A comprehensive documentation on the project code will be uploaded as soon as I finish translating it (~1-2 months, sorry, I'm really busy right now).