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In System Programming via JTAG port: Overview Details Name: isp Created: 22-Jun-2006 22:57:55 Updated: 19-Jul-2008 07:08:12 CVS: no files in cvs Other project properties Category :: Other Language :: Verilog Development status :: Planning Project maintainers Zeng bo Statistics view Description The aim of this project is to make a simple way to program a parallel memory mounted on pcb. Now, there is usually an fpga or a cpld in your pcb design. There are also some memories, such as flash or eeprom. This project will tell u how to program the memories in isp mode through a cpld or fpga. Here, we choose the flash w29ee011-90, the cpld xc95216-10. The design can access 16M memory. And We will add an FPGA configuration circuit to the design, so the design can be used to config a large FPGA. Roadmap Step 1: Using xc95216 to program w29ee011. 1.1 an isp module fitting the timing of w29ee011. 1.2 a jtag pc program fitting the timing of w29ee011. Step 2: an isp module fitting more flash or eeprom, Status preparing to release the design...... testing the design on PCB ---- 2007.11 design PCB for testing ---- 2007.8 verifying the module ----2007.5 developing verilog code of JTAG-ISP ciruit ----2006.10 developing Visual C + code of JTAG software ----2006.6