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HDLC controller: Overview Details Name: hdlc Created: 25-Sep-2001 10:15:03 Updated: 14-Nov-2001 21:34:48 CVS: browse Other project properties Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Jamil Khatib Statistics view Features 8 bit parallel backend interface use external RX and TX clocks Start and end of frame pattern generation Start and end of frame pattern checking Idle pattern generation and detection (all ones) Idle pattern is assumed only after the end of a frame which is signaled by an abort signal Zero insertion Abort pattern generation and checking Address insertion and detection by software CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) FIFO buffers and synchronization (External) Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) Q.921, LAPB and LAPD compliant. For complete specifications refer to spec document Core top block diagram Status The VHDL code is ready in the opencores CVS. The code needs verification contact me if you are intrested in helping me. also see Download section Resource usage Rx Channel Block: which includes HDLC Framing extraction, zero removal and conversion from serial to parallel. Vendor Device Size Frequency  Board Tested Functional Test Notes Altera EP20K100BC356-3 108 LCs 91.48MHz - - No optimization was peroformed, using Quartus II Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. Vendor Device Size Frequency  Board Tested Functional Test Notes Altera EP20K100BC356-3 100 LCs 112.42MHz - - No optimization was peroformed, using Quartus II HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. Vendor Device Size Frequencies (MHz) Board Tested Functional Test Notes Altera EP20K100BC356-3 630 LCs, 2 ESBs CLK_I=74.02, RxClk=101.86, TxClk=106.42 - - No optimization was peroformed, using Quartus II Links http://www.rad.com/networks/1994/hdlc/hdlc.htm http://www.erg.abdn.ac.uk/users/gorry/course/dl-pages/hdlc-framing.html http://members.tripod.com/~vkalra/hdlc.html http://goanna.cs.rmit.edu.au/~ivan/cs361/lec/lec5.pdf http://www.inicore.com/____pdf/inihdlc.pdf http://www.mentorg.com/inventra/netlist_program/actel/ds/hdlccoreA1_pd.pdf