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    Overview :: News :: Downloads :: Tracker :: Discussions (cores)    

    Configurable Hamming Generator: Overview

    Details

    Name: hamming_gen
    Created: 27-Oct-2006 22:55:27
    Updated: 21-Aug-2007 18:28:00
    CVS: no files in cvs

    Other project properties

    Category :: ECC core
    Language :: VHDL
    License :: GPL
    Development status :: Production/Stable

    Project maintainers

  • Alexandre Amory
  • ghanashyam prabhu
  • Statistics

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  • Opened bugs

  • project has opened bugs
  •    


    Description

    This C++ program generates VHDL package with hamming encoder and decoder. It also generates a simple testbench that can be used to evaluate the generated Hamming code.

    my email is ale_amory@o...

    Features

    • It is a easy to use command-line program
      • HammingGen <SEC/SEC-DED> <data width> <project_name>
    • It generates two types of Hamming code
      • SEC - Single Error Correction
      • SEC-DED - Single Error Correction and Dual Error Detection
    • It is easy to modify the original design

    Examples

    Generated Code for a Hamming SEC with 32 bits

    • FUNCTION hamming_encoder_32bit(data_in:data_ham_32bit) RETURN parity_ham_32bit;
    • FUNCTION hamming_decoder_32bit(data_parity_in:coded_ham_32bit) RETURN data_ham_32bit;
    Consider the folowing resgister description

    library ieee;
    use ieee.std_logic_1164.all;

    entity test is
    port (
    datain : in std_logic_vector(15 downto 0);
    clock : in std_logic;
    dataout : out std_logic_vector(15 downto 0);
    error : out std_logic_vector(1 downto 0)
    );
    end entity;

    architecture test of test is
    signal temp : std_logic_vector(15 downto 0);

    begin

    process(clock)
    begin
    if (clock'event and clock='1') then
    temp <= datain;
    end if;
    end process;

    dataout <= temp;

    end architecture;


    The fault-tolerant version of this code is:

    library ieee;
    use ieee.std_logic_1164.all;
    use WORK.hamm_package_16bit.all;

    entity test is
    port (
    datain : in std_logic_vector(15 downto 0);
    clock : in std_logic;
    dataout : out std_logic_vector(15 downto 0);
    error : out std_logic_vector(1 downto 0)
    );
    end entity;

    architecture test of test is
    signal temp : coded_ham_16bit;

    begin

    process(clock)
    begin
    if (clock'event and clock='1') then
    temp <= datain & hamming_encoder_16bit(datain);
    end if;
    end process;

    dataout <= hamming_decoder_16bit(temp);

    end architecture;

    Future Features

    • Support correction of more than one faults


     

     
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