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FPU: Overview
Description
This is a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Features
- FPU supports the following arithmetic operations:
- Add
- Subtract
- Multiply
- Divide
- Square Root
- For each operation the following rounding modes are supported:
- Round to nearest even
- Round to zero
- Round up
- Round down
- Pipelined to achieve high operating frequency (100MHz with Cyclone EP1C6)
- Tested with 2 million test cases
- Hardware proven: FPU was implemented in a Cyclone I–EP1C6 FPGA chip and was then connected to the Java processor JOP(jopdesign.com) to do some floating-point calculations.
For more details please read the documentation. If that doesn't help, then post your question here: http://groups.yahoo.com/group/32bit_fpu/
Status
- 30-Jan-2006: Uploaded project (files will be imported into CVS very soon)
- 02-Mar-2006: Added CVS files
- 28-Mar-2006: Tested the FPU with 2 million test cases and corrected two bugs. [fpu_v14]
- 28-Mai-2006: 1)Intializing bug fixed in testbench; 2)Extended 1 clock cycle more for multiplication, becasue of an Intializing issue.[fpu_v15]
- 14-Jun-2006: 1)Corrected an embarrassing syntax error in "tb_fpu.vhd": start_i <= 0 to start_i <= '0'; 2)In "serial_div.vhd" and "sqrt.vhd": unused bits in some signals were initialized.; 3)Not needed line in "fpusim.bat" was removed.[fpu_v16]
- 16-Jul-2006: 1)Corrected bug related to adding two denormalized operands.[fpu_v17]
- 22-Jul-2006: 1)post_norm_addsub.vhd: Restructured and fixed a bug; 2)fpu.vhd: Altered add/sub COUNT; 3)tb_fpu.vhd: Added some boundary values. [fpu_v18]
- 26-Apr-2007: 1)A minor bug was found and corrected when the serial multiplier is used (thanks to Chris Basson!). [fpu_v19]
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