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FirGen/MultGen: VHDL Core Generator for FIR filters and Multiplier arrays Details Name: fir_filter_generator Created: 29-Dec-2005 02:30:02 Updated: 28-Mar-2008 07:10:26 CVS: no files in cvs Other project properties Category :: DSP core Language :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Boris Kipnis Statistics view Description VHDL core generator FIRGEN Project generates optimized VHDL codes for FIR Filters and Multiplier arrays using "Nonrecursive Signed Common Subexpression Algorithm". program writen on C++ -------------------------- firgen [OPTION..] Available options are : -w Input Data Width -m Generate Only Multipliers Array -a Generate Asynchronus Multipliers array (no CLK signal) -e Use CLK_EN input -c filter coefficients, coma separated -o Output File Name -? Help Example For Use: ---------------- FirGen -w 16 -c 1,2,3,4,5 -o my_fir this command generates 2 output files my_fir.vhd - Main Fir module my_fir_mult.vhd - Multipliers Array (DIn*C1, DIn*C2,..., DIn*Cn) Input data width is 16 bit Filter Coefitions : 1,2,3,4,5 Features FIR Filter Generator Multiplyer Array Generator with common input Status Stable and ready for use Ver1.1 Asynchronus operation and CLK_En features added ------------------------------------------------------------------ Download URL: http://www.opencores.org/pdownloads.cgi/list/fir_filter_generator ------------------------------------------------------------------ note : May be you will need to install cygwin from www.cygwin.com to be able run this program.