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extension_pack: Overview Details Name: extension_pack Created: 06-Jan-2006 06:34:53 Updated: 14-Sep-2006 12:35:46 CVS: browse Other project properties Category :: Library Language :: VHDL Phaze :: Design done Development status :: Production/Stable Project maintainers Michael Bills Statistics view Project Type VHDL Library Description This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code. Features automatic count stop/start value generation functions. You enter a time duration and clock frequency and the value is automatically computed. Your choice of binary or LFSR number spaces. LFSR counters created by function call. clock generation procedures type and number conversion functions: synthesizable binary_to_BCD and BCD_to_binary functions synthesizable BCD_to_seven_segment display functions string value to std_logic_vector: "32" -> "0100000" Status Production Ready. Please let me know of ANY problems you find.