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Linux & Xilinx FPGA Dev Board: Overview
Description
EUS 100LX is an "open" system board conforming to the PC104 format (90,2mm x 95,9mm) designed for industrial control and data acquisition applications. It is equipped with CPU, gate array and support electronics and comes with Linux operating system version 2.4 or 2.6, driver for communication with FPGA and peripheral devices, Allegro graphics library. Example FPGA cores are available in source form, as well as full board documentation - schematics, layout (available at http://www.dspfpga.com/?page=eus_100lx).
Block Diagram
Features
- ETRAX 100LX / MCM416 CPU
- 32 MB SDRAM, 8 - 64 MB Flash
- FPGA Spartan 3-XC3S400 - 1500, connected directly on CPU bus
- support for partial reconfiguration without readback
- dedicated independent SDRAM for FPGA - 16MB
- power management, watchdog, temperature and voltage sensors implemented in MSP430 microcontroller
- 10/100Mb Ethernet port
- 2 x USB 1.1 port
- 1 x RS232 port for ETRAX and MSP (may be extended upto 4 ports)
- JTAG interface for FPGA (Parallel Cable IV connector) and MSP
- character LCD display supported including programmable backlight and contrast control
- TFT LCD supported via linear framebuffer core, VGA support planned
- 14 LVDS pairs or 28 LVTTL IOs
- 90 separate input/output signals from FPGA, 5V tolerant
- 94 general IO from ETRAX, MSP and FPGA
- single power suplly voltage: 5V @ 600mA (depends on configuration and USB device consumption)
- port of Allegro graphics library
- boot over ethernet
- FPGA initialization and communication tools
- OS Linux, ftp, web, telnet
- all source code licensed under GPL or OHGPL
- royalty free application development software
Pictures
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Bottom Side |
Status
- Schematic: done
- PCB Layout: done
- PCB Assembly & Testing: done
- Linux 2.4: done
- MCU Software: done
- FPGA Boot & Communication utility: done
- FPGA Codes adn Examples: starting - available soon
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