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10_100_1000 Mbps tri-mode ethernet MAC: Overview
Project Status
- collect some documents about tri-mode ethernet MAC controller(done)
- coding in verilog(done)
- coding verification scripts(done)
- starting verification(done)
- writing specification(done)
- FPGA proven(done) 2006-06-20
- Supporting modelsim simulator. I also changed the default simulator from NC-sim to modelsim which is much populor than NC-sim :->. As well, the new version "dll" files for modelsim are ready. (done) 2008-7-26
- My next task is to connect this IP core to xilinx Microblaze processor.(done)2008-8-17
A new directory EDK was created in project root. All needed driver and EDF for EDK are available there.
Description
10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The whole project will be finished in TEN weeks inluding verilog coding,RTL level verification.
A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.
main Features
Ø Implements the full 802.3 specifiction.
Ø half-duplex support for 10 100 Mbps mode
Ø FIFO insterface to user application
Ø support pause frame generation and termination
Ø transmitting frames souce MAC address insertion
Ø receiving frames destination MAC address filter
Ø receiving broadcast frames throughout constraint
Ø support Jumbo frame 9.6K
Ø RMON MIB statistic counter
Synthesis area report
##### START OF AREA REPORT #####
I/O ATOMs: 321 Total LUTs: 1839 of 10570 (17%)
Logic resources: 1839 ATOMs of 10570 (17%)
ATOM count by mode:
normal: 1555
arithmetic: 284 DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 6 blocks (48 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 1)
M4Ks: 0 (0% of 60)
M512s: 0 (0% of 94)
Total ESB: 0 bits
##### END OF AREA REPORT #####]
verification report
1. 1G mode ,46-1500 length packet sending and receiving was tested
2. 100M mode, 46-1500 length packet sending and receiving was tested
3. 10M mode , 46-1500 length packet sending and receiving was tested
place and route report
Logic Utilization:
Number of Slice Flip Flops: 1,198 out of 21,504 5%
Number of 4 input LUTs: 1,526 out of 21,504 7%
Logic Distribution:
Number of occupied Slices: 1,206 out of 10,752 11%
Number of Slices containing only related logic: 1,206 out of 1,206 100%
Number of Slices containing unrelated logic: 0 out of 1,206 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 1,555 out of 21,504 7%
Number used as logic: 1,526
Number used as a route-thru: 29
Number of bonded IOBs: 78 out of 448 17%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 2
Number used as BUFGCTRLs: 3
Number of FIFO16/RAMB16s: 4 out of 72 5%
Number used as FIFO16s: 0
Number used as RAMB16s: 4 Total equivalent gate count for design: 20,650
Additional JTAG gate count for IOBs: 3,744
Peak Memory Usage: 220 MB
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