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    Overview :: News :: Downloads :: Tracker :: Discussions (cores)    

    Ethernet Development Board: Overview

    Details

    Name: ethdev
    Created: 30-Aug-2005 22:19:55
    Updated: 10-Nov-2005 16:58:34
    CVS: no files in cvs

    Other project properties

    Category :: Prototype board
    Phaze :: FPGA proven
    Development status :: Production/Stable

    Project maintainers

  • Jai Dhar
  • Statistics

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  • Description

    Note: I have just released a new version, v 1.0C. Minor bug fixes have been introduced. Visit my page for more info!

    Ethernet Development prototyping board featuring Altera Cyclone 12Q240 FPGA.

    This board was designed primarily to get me started into Ethernet development. It has served that purpose, as well as given me a good prototyping board for general purpose usage. It is relatively low-cost, and is limited mainly by the cost of the FPGA. The other components are quite cheap in general. The Ethernet section features a 10/100 National Semi. PHY that works with FPGA MAC's such as the Open cores Ethernet project.

    The board is both NIOS-ready and Altium Protel-ready.

    All files are open to the public on my web site (below), however, if you wish to obtain a board, you can contact me for either the bare PCB or a ready-made version.

    Block diagram of board:


    Actual picture of board:



    Features

    Web site: http://www.fps-tech.net
    Schematic: http://via.dynalias.org/hw/EthDev/MFG1-0C/doc/Schematic%20Prints.pdf
    User guide: http://via.dynalias.org/hw/EthDev/MFG1-0C/doc/ethdev-ug.pdf

    * Altera Cyclone 12Q240 FPGA. I currently have a 12Q240I7 loaded on my board.
    * 2x 256K x 16 fast SRAM (12 ns access) - can be combined for 256K x 32 or 512K x 16 <- these can also be upgraded.
    * 5V IO interface (8 5V input signals, 8 bi-directional)
    * I2C Peripherals - RTC, 512 Kbit, Temperature sensor
    * Bank of 8 LED's, 4 push-buttons, 1 reset button
    * Nexus JTAG header - 4 Hard JTAG signals and 4 soft JTAG signals
    * Altera byteblaster II JTAG header - can also be used to program board
    * National Semiconductor Ethernet 10/100 PHY with RJ45 jack (integrated magnetics)
    * 16 General purpose IO header
    * 1 PLL output header
    * 2 PLL clock oscillator inputs
    * 1 RS232 port
    * 5.5" x 4" double-sided PCB
    * 4 MBit EPCS Flash programmer
    * 32 Mbit SPI Flash for additional code storage
    * Processors: This board has been tested with the Altera NIOS processor, Protel TSK 3000 and TSK 51 processors. Various cores that have been successfully are the Ethernet Opencore and the SPI opencore.


     

     
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