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Embedded 32-bit RISC uProcessor with SDRAM Controller: Overview Details Name: embedded_risc Created: 08-Apr-2002 21:49:20 Updated: 26-Jul-2002 09:14:55 CVS: browse Other project properties Category :: SoC Development status :: Planning Project maintainers Hossein Amidi Statistics view Description Embedded 32-bit mini RISC uProcessor project with SDRAM controller will develope a basic block IP (Intellectual Properties) for designing a complete SOC (System On a Chip) system. Today almost in every Advanced Digital products you will find a few uController or uProcessor. Both of these cathegories needs a processing power to recieve some sord of input or data and needs to process it for the end application or perhaps to store the input/data. In order for the system to process or perhaps store the incoming data it needs to distinguish between the incoming command and data itself. This can be done by either a simple FSM (Finite State Machine) or a more complex circuitry such as a uProcessor. uProcessor need a space to store it's code and a seperate space to store it's temorary data informations. For this project since the entire system would be in a single chip I will create a SDRAM (Synchronous Dynamic Random Access Memory) controller which will recieve the uProcessor read and write command and translated into the approprite device cycles for SDRAM devices, SDRAM will be used to store the temporary Data. Also there would be an interface for the Flash memory to store our codes. The embedded uProcessor for our SOC project would be a 32-bit RISC (Reduced Instruction Set Computer) which allows all the Instructions to be executed in a single clock cycle. Embedded 32-bit mini RISC uProcessor for this project would have a five stage pipeline as follow: 1) Fetch the Instruction 2) Decode the Fetched Instruction 3) Execute the Decoded Instruction 4) Check the Flag and Interrupts 5) Write to Register File Furthermore the SOC would have the following peripherals: . Bus Arbiter . Serial-to-Parallel Converter . Set Associative, two-way LRU Cache . DMA . PIO Interface . Timer . Watch-Dog Timer Features * 32-bit mini RISC uProcessor with SDRAM Controller * PC100 CL2 100 Mhz SDRAM Controller * Supports up to 8MB SDRAM for Data Storage * Supports up to 512KB Flash for Code Storage Repository: CVS:embedded_risc Status • Preliminary Architectural Block Diagram defining of the SOC Project is being prepared. 09/04/2002 • Preliminary Architectural Block Diagram defining of the SOC project has been finished. 05/06/2002