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Parameterisable DRAM model: Overview Details Name: dram Created: 25-Sep-2001 10:15:02 Updated: 27-Apr-2005 12:05:03 CVS: not found! Other project properties Category :: Memory core Development status :: Production/Stable Statistics view Opened bugs project has opened bugs Description Parameterisable DRAM model, i.e. scalable data and address widths. Simulation assertions can be toggled on/off. Uses !RAS/!CAS control sequence for modelling DRAM activity. Refresh is monitored with data corrupted to "UU ... " Status VHDL code is available (see Downloads) Author Damon P Thompson