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Hardware Division Units: Overview Details Name: divider Created: 28-Oct-2002 14:12:13 Updated: 20-Jan-2004 10:12:34 CVS: browse Other project properties Category :: Arithmetic core Development status :: Production/Stable Project maintainers Richard Herveille Statistics view Description This is a collection of synthesizeable hardware dividers. Different types of dividers are available. All dividers are fully pipelined and provide a 2N by N division every clock cycle. All designs are fully parameteriseable and synthesizeable. The dividers take two inputs Z(2N-bit divident) and D(N-bit divisor), and return Q(N-bit quotient), S(N-bit remainder), div0(division by zero), and ovf(overflow). A sample implementation of a 32/16 bit divider with a remainder output runs at about 82MHz in a Spartan2e100 -6 device and occupies 1132 LUTs (about 47%) and 1736 registers (about 72%) of the device. Features Fully synthesiseable Fully parameteriseable Pipelined design (one pipeline stage per bit) provides a result every clock cycle. Includes testbench Status The following division units are ready and available for download: Non-restoring unsigned by unsiged divider Non-restoring signed by unsiged divider