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Diogenes: Student RISC System: Overview Details Name: diogenes Created: 01-Feb-2008 15:24:17 Updated: 04-Feb-2008 19:26:01 CVS: browse Other project properties Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Beta Project maintainers Andreas Fellnhofer Statistics view Description This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture. Please note that it was developed on a Sparten-3E Starter Kit and memory in VHDL code is embedded via XILINX specific routines. Features Assembler Simulator Simple I/O (Leds, Buttons, UART, Hitachi LCD) VGA Controller Status presented in class as working