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cpu6502_tc: Overview Details Name: cpu6502_true_cycle Created: 23-Jan-2008 06:23:02 Updated: 17-Apr-2008 21:21:47 CVS: browse Other project properties Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Jens Gutschmidt Statistics view Description This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetch. The ready signal is usable for DMA operations or multiprocessing. Signal sync can be used for software/hardware debugging via single stepping (single cycles or complete op codes) the 6502. This core was successfully tested in an APPLE ][+ SoC (completely designed into a FPGA with Z80 Softcard, DISK2 System, 80C Card, Language Card and 48kB of main memory). Please feel free to contact me for any reasons like ideas or error messages. Features true cycle timing for all official opcodes unknown op's decoded as "NOP/0xEA" one clock source input signal "rdy_i" for generating waitstates (see original documentation of R6502) output signal "sync_o" to indicate an op fetch (see original documentation of R6502) input signal "so_n_i" sets the internal OV Flag (see original documentation of R6502) running up to 40MHz or faster on Altera's Stratix/StratixII fully synthesizable VHDL Status *** ATTENTION: Bugfixes available - see below and the tracker ************* CORE: Ready for use and downloadable via CVS LICENSE: Puplished under GPL V3 DOCUMENTATION: "on working" TESTBENCHES: "on working" TESTSOFTWARE: "on working" CHANGES made at 17-Apr-2008: State of project CVS loaded with new core and HTML documentation correct the handling of the stack while BRK, IRQ and NMI correct the handling of "B" flag while BRK correct the alignment between addresses and data while BRK, IRQ and NMI when writing onto the stack QUALITY of cpu6502_tc: all op codes: simulated and approved under real working conditions (APPLE ][plus SoC) BRK command incorrecly implemented at 11-Apr-2008 (fixed now) irq_n_i: only simulated - incorrecly implemented at 11-Apr-2008 (fixed now) nmi_n_i: only simulated - incorrecly implemented at 11-Apr-2008 (fixed now) so_n_i: not simulated yet all other signals: simulated and approved under real working conditions (APPLE ][plus SoC)