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radix 4 complex fft: Overview Details Name: cfft Created: 29-Oct-2002 12:22:18 Updated: 11-Sep-2003 12:19:05 CVS: browse Other project properties Category :: Arithmetic core Development status :: Production/Stable Project maintainers ZHAO Ming Statistics view Description This is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly. A sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device. Features Data width configurable Point configurable Input data during data output Simulation result has compare with Matlab result Status Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget ...