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CF State Space Processor: Overview Details Name: cf_ssp Created: 15-Apr-2003 17:36:31 Updated: 08-May-2008 08:35:35 CVS: no files in cvs Other project properties Category :: Microprocessor Development status :: Production/Stable Project maintainers Tom Hawkins Statistics view Description Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent.org for more info. Several cores are provided in Verilog, Vhdl, and C. If you don't see the configuration you need, chances are we can easily generate it for you. The State Space Processor is used for implementing discrete linear systems, such as finite and infinite impulse response filters, multiple input and output systems, and general state space equations common in control and DSP applications. Its simple instruction set and efficient architecture has a very low logic footprint. Features Architecture: The processor requires two external memories: one for program instructions and the other for constants (coefficients) used in calculation. The processor maintains a register file of 16 N-bit registers used to retain state information and for processing intermediate results. The register file is also used for handling input and output; registers can be written from an external source and all registers are available as outputs. For convenience, register 0 is wired to ground and instructions updating r0 have no effect on the register file. The processor runs calculations on a cycle basis: 1. The external environment writes inputs into the register file. 2. The external environment signals a "Cycle" to run the program and calculate a cycle. 3. The external environment waits for "Done", then reads output from the register file. Instruction Set: There are 4 instruction types and a total of 8 instructions. Each instruction is 16-bits. The types include: Unary Operation OpCode [15:12], Operand A Reg [11:8], Not Used [7:4], Result Reg [3:0] Binary Operation OpCode [15:12], Operand A Reg [11:8], Operand B Reg [7:4], Result Reg [3:0] Constant Load OpCode [15:12], Constant Memory Address [11:4], Result Reg [3:0] Halt OpCode [15:12], Not Used [11:0] Unary Operations (OpCode): ShiftLeft (0000) RegX <- lsbs RegA '+' '0' Flag <- Flag ShiftRight (0001) RegX <- msb RegA '+' msbs RegA Flag <- lsb RegA ShiftClip (0010) RegX <- lsbs RegA '+' '0' when top 2 bits of RegA == '00' or '11' RegX <- '0111...1' when top 2 bits of RegA == '01' RegX <- '1000...0' when top 2 bits of RegA == '10' Flag <- Flag Performs a limited/clipped multiplication by 2. Binary Operations (OpCode): Add (0011) RegX <- RegA '' RegB Flag <- msb Result AddCond (0100) RegX <- RegA '' RegB when Flag else RegA Flag <- Flag Sub (0101) RegX <- RegA '-' RegB Flag <- msb Result Switch (0110) RegX <- RegA when Flag else RegB Flag <- Flag Constant Load Instruction (OpCode): Constant (0111) RegX <- Data from constant memory. Flag <- Flag Halt Instruction (OpCode): Halt (1---) Halts processor (prevents further register updates). Booth multiplication can be performed using ShiftRight and AddCond with an accumulation register. Each file is stand-alone and represents a specific configuration. The 2 parameters are: Data Width Instruction Memory Address Width The configuration parameters are coded in the file names: cf_ssp_32_5.v 32 : Data Width 5 : Instruction Memory Address Width Current configurations: cf_ssp_8_6 cf_ssp_16_6 cf_ssp_32_6 cf_ssp_64_6 cf_ssp_8_7 cf_ssp_16_7 cf_ssp_32_7 cf_ssp_64_7 cf_ssp_8_8 cf_ssp_16_8 cf_ssp_32_8 cf_ssp_64_8 cf_ssp_8_9 cf_ssp_16_9 cf_ssp_32_9 cf_ssp_64_9 cf_ssp_8_10 cf_ssp_16_10 cf_ssp_32_10 cf_ssp_64_10