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CF FIR Filter: Overview Details Name: cf_fir Created: 30-Mar-2003 13:22:46 Updated: 08-May-2008 08:33:05 CVS: no files in cvs Other project properties Category :: DSP core Development status :: Production/Stable Project maintainers Tom Hawkins Statistics view Description Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info. Finite impulse response (FIR) filters are common in DSP applications and consist of a delay bank (filter taps) and a sum-of-products. Features The filter architecture consists of a delay bank and a pipelined sum-of-products network. All arithmetics are lossless -- multipliers produce precision with the sum of the operands and each adder extends precision by 1 bit. The filter has a synchronous reset to reinitialize the filter taps. The reset does not affect the pipeline registers in the sum-of-products network. The filter includes ports for the filter coefficients; typically hardwired to constants. Each file is stand-alone and represents a specific configuration. The 3 configuration parameters are: Filter Order (# of delay taps) Input Precision Coefficient Precision The configuration parameters are coded in the file names: cf_fir_3_16_8.v 3 : Filter order. 16 : Input precision. 8 : Coefficient precision. Current configurations: cf_fir_3_8_8 cf_fir_7_16_8 cf_fir_7_16_16 cf_fir_12_16_10 cf_fir_16_16_16 cf_fir_24_8_8 cf_fir_24_16_16 cf_fir_33_16_16