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Biquad IIR Filter Core: Overview
| Details Name: biquad
Created: 25-Sep-2001 10:15:02
Updated: 14-Oct-2001 20:33:53
CVS: no files in cvs Other project properties Category :: DSP core
Development status :: Production/Stable
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Specifications
- IIR filter with two poles and two zeros
- Data width set by user
- Coefficient width set by user up to 16 bits
- Wishbone interface for read and write of filter coefficient registers
- Multiple filters can be combined to form filters with more than two poles and zeros
Description
The difference equation for the biquad filter is: y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2] This equation is implemented as shown below:
Synthesis
Synthesized with Synopsys FPGA Express version 2000.11-FE3.5.
If you use this core please let me know.
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