LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Downloads :: Tracker :: Discussions (cores)    

    BigCounter: Overview

    Details

    Name: big_counter
    Created: 20-Dec-2007 07:46:15
    Updated: 02-Jan-2008 10:56:55
    CVS: browse

    Other project properties

    Category :: Other
    Language :: VHDL
    License :: GPL
    Development status :: Beta

    Project maintainers

  • Andrew Mulcock
  • Statistics

  • view
  • Description

    Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic

    Features

    Designed for Xilinx FPGA's, with SRL's.

    An efficient way of generating a divide by n**16 counter, where N can be very big.

    Status

    basic counter in cvs


     

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.